This invention relates to sense amplifiers, and more specifically to an improved sensing circuit and method which reduces the occurrence of invalid data being transmitted to an output data bus.
Timing performance is key to many memory devices. To minimize delay, current methodologies enable memory sense amplifiers prior to new data arriving at the inputs of the sense amplifier. With such an approach, data is sensed immediately upon receipt at the sense amplifier inputs, then driven onto an output data bus. Typically, the data is also stored in a latch or register so that the sense amplifier and the remaining memory circuitry can be powered down or prepared for the next operation cycle while maintaining the data on the output data bus.
With current methodologies, there are numerous ways in which invalid data transitions can be sent to the output data bus before the next valid data appears. These invalid transitions consume AC power, which in low power systems can be significant. One potential source of invalid data is the sense amplifier. Between the time that a sense amplifier is activated and the moment when new data arrives from the memory array, the sense amplifier will try to sense what is appearing at its inputs and will begin to send what is sensed (e.g., invalid data) to the output data bus. If the polarity of what is appearing at the sense amplifier inputs is opposite from the polarity of the data that is appearing on the output data bus and the data to be sensed from the memory array to the sense amplifier inputs, the output data bus will transition from the previous data on the bus, to the invalid data (the data sensed during the time between the sense amplifier being enabled and valid data appearing at its inputs), and finally to the newly sensed valid data.
Another potential source of invalid data is the data storage device of the sense amplifier. When the sense amplifier is activated, the data being stored in the storage device from a previous operation can be sent to the output data bus. If the data being stored from the previous operation is opposite in polarity from what is appearing on the output data bus and from the data to be sensed from the memory array, there will be glitch on the output data bus; meaning, the output data bus will transition from the valid data that was appearing on the bus to the data stored in the storage device from a previous operation then to the newly sensed data from the memory array.
Yet another potential source of invalid output data bus transitions can arise where the memory device is but one of many structures of a larger system that supplies data to the output data bus. When the memory device is activated, there is no guarantee as to what signals will be driven onto the output data bus prior to the sense amplifier sensing the valid data from the memory array and providing that valid data to the output data bus.
One known approach to dealing with invalid output data transitions is simply accept the invalid transitions and any corresponding AC power drain they may cause. This is typically done by setting up the overall system timing around possible occurrences of the invalid transitions. Another known approach to dealing with invalid output data transitions appearing on the output data bus is to design delayed timing paths around the sensing and output driving circuitry of the memory device. Data is typically gated from the memory array to the sense amplifier and from the data storage device to the output drivers. Depending upon the requirements of a particular design, data may also be gated between the sense amplifier and the data storage device. Each gate is opened only after a sufficient period time has elapsed to ensure that the data appearing at the inputs of each gate has stabilized. Because it is difficult to predict precisely when stabilization occurs at each stage, the delays must be set up to mimic the worst case timing paths. Additional delay must also be included to account for fabrication and device or process variations that could adversely impact timing performance.
The known approaches fall short with the increasing need for speed, precision, and low power consumption in products such as cellular phones, pagers, and other portable communication devices and particularly, in low voltage applications. Accordingly, it would be advantageous to have a method and circuitry for sensing data from a memory array and dealing with glitches on the output data bus that did not adversely impact the operating speed. It would be a further advantage to have a method and apparatus for eliminating invalid data transitions from appearing on the output data bus. It would further be advantageous for such methods and circuitry to minimizes the power consumption and thereby conserve battery life in portable applications.